Chennai Mathematical Institute

Seminars




11:45, Seminar Hall
Some Lower Bound Results for Set-Multilinear Arithmetic Computations

S. Raja
Institute of Mathematical Sciences, Chennai.
28-03-16


Abstract

In this work, we study the structure of set-multilinear arithmetic circuits and set-multilinear branching programs with the aim of showing lower bound results. We define some natural restrictions of these models for which we are able to show lower bound results. Specifically, our main results are the following:

(1) We observe that set-multilinear arithmetic circuits can be transformed into shallow set-multilinear circuits efficiently, following [VSBR83,RY08]. Hence, polynomial size set-multilinear circuits have quasi-polynomial size set-multilinear branching programs.

(2) We show that \emph{k-narrow} set-multilinear ABPs computing the Permanent polynomial $PER_n$ (or determinant $DET_n$) require $2^{\Omega(k)}$ size. As a consequence, we show that sum of $r$ read-once oblivious ABPs computing $PER_n$ requires size $2^{\Omega(\frac{n}{r})}$.

(3) We also show that set-multilinear branching programs are exponentially more powerful than \emph{interval} multilinear circuits (where the index sets for each gate is restricted to be an interval w.r.t. some ordering), assuming the sum-of-squares conjecture. This further underlines the power of set-multilinear branching programs.

(4) Finally, we show exponential lower bounds for set-multilinear circuits with restrictions on the number of parse trees of monomials and prove exponential lower bounds results.

This is a joint work with V. Arvind.

ECCC link: http://eccc.hpi-web.de/report/2015/176/





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