Chennai Mathematical Institute

Seminars




12:00 noon, Seminar Hall
Hardware Support for Shared-memory Concurrency: Reconciling Programmability with Performance

Vijay Nagarajan
University of Edinburgh, UK.
05-01-16


Abstract

With regard to shared-memory concurrency, an inherent tradeoff between programmability and performance is presumed. For instance, the most intuitive memory consistency model, sequential consistency (SC), is presumed to be too expensive to support; likewise primitive synchronization operations like memory fences and atomic read-modify-writes (RMWs) (which are used as the building blocks of higher level synchronization constructs) are costly in current processors; finally, there are question marks about whether cache coherence will scale with increasing number of cores.

In this talk, I will argue that it is indeed possible to provide hardware support that enhances programmability without sacrificing performance. Our key insight is semantics-directed design: hardware design should be guided by precise formal specifications instead of ad-hoc informal ones. Indeed, I will show how SC can be enforced efficiently using conflict ordering, a novel technique for achieving memory ordering. Second, I will show how RMWs can be implemented efficiently in x86 architectures. Third, I will illustrate a scalable approach to cache coherence called consistency-directed coherence. i will conclude the talk with how I believe semanticists and hardware designers can work together to create correct and efficient hardware designs.





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